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<body background="images/res_bkg.jpg" bgproperties="fixed" stylesrc="resume.html"> <p><marquee align="middle" behavior="slide" bgcolor="#FFFFFF" width="90%">Software and EDA Tools Development</marquee></p> <hr> <div align="center"><center><table border="0"> <tr> <th><h1><font color="#800000"><u>Stephen A. Bailey</u></font></h1> </th> </tr> <tr> <td align="center">6664 Cherokee Ct.<br> Niwot, CO 80503</td> </tr> <tr> <td align="center">303-652-1578 (voice & fax)</td> </tr> <tr> <td align="center"><a href="mailto:stephen@srbailey.com"><img src="images/mailbutt.gif" width="34" height="37"></a></td> </tr> </table> </center></div><hr> <div align="center"><center><table border="1"> <caption align="top"><a name="resume-index">Resume Contents </a></caption> <tr> <td><a href="#resume-edu">Education</a></td> </tr> <tr> <td><a href="#resume-skills">Skills Overview</a></td> </tr> <tr> <td><a href="#resume-emp_history">Employment History</a></td> </tr> <tr> <td><a href="#resume-pubs">Publications</a></td> </tr> </table> </center></div><hr> <h2><a name="resume-edu">EDUCATION</a></h2> <dir> <li><a name="resume-edu">M.S. Computer Science, Chapman College, 1989. </a></li> <li><a name="resume-edu">B.S. Computer Science, (magna cum laude) Chapman College, 1986. </a><p><a name="resume-edu">Return to </a><a href="#resume-index">Index </a></p> <hr> <h2><a name="resume-skills">SKILLS SUMMARY</a></h2> </li> <li><a name="resume-skills">Hardware and Software Tools Development: VHDL simulation, compilers, CASE </a></li> <li><a name="resume-skills">Multi-threaded applications. </a></li> <li><a name="resume-skills">Object-oriented design and programming </a></li> <li><a name="resume-skills">Software build, regression and configuration management (Atria Clearcase) </a></li> <li><a name="resume-skills">Project management experience with teams from 2 - 8 engineers. </a></li> <li><a name="resume-skills">Languages : VHDL, C++, C, Ada. </a></li> <li><a name="resume-skills">Platforms : UNIX (Sun, IBM, HP), SMP (Sun/SGI), DOS and MS-Windows. </a></li> <li><a name="resume-skills">Customer Support: worked with customers to resolve VHDL language and tool usage . </a></li> <li><a name="resume-skills">Technical Writing: Technical proposal authoring, users manuals, papers and presentations </a></li> <li><a name="resume-skills">Industry Standards: IEEE-Std-1076-1993 (VHDL '93), shared variable working group chair . </a><p><a name="resume-skills">Return to </a><a href="#resume-index">Index </a></p> <hr> <h2><a name="resume-emp_history">EMPLOYMENT HISTORY</a></h2> <h3>SRBailey Consulting, Campbell, CA, 5/95 - Present, Owner</h3> <ul> <li>VHDL Simulator Development (5/95 - Present): Analysis, design and implementation of a VHDL '93 elaborator. </li> </ul> <ul> <li>VITAL Modelling (5/95 - 6/95): Re-implemented ASIC library cells in VITAL 3.0 format. Originally, the cells were modelled in a proprietary gate-level VHDL style. Verified correct functionality and timing via testbenches which instantiated both VITAL and proprietary cells comparing the outputs of each based on identical stimuli. </li> </ul> <h3>Vantage Analysis Systems (Viewlogic), Fremont, CA, 3/92 - 5/95, Project Manager</h3> <p>Managed five different projects with teams ranging in size from 2 to 8 engineers. DOS and Win32s port of VHDL simulator. Current project; one engineer porting source, build and regression processes; defining platform-specific capabilities. Multi-threading VHDL simulator. Current project; one engineer. Sun Solaris platform. Product has shown 2 to 4x performance with 4 to 8 threads. Continue optimizations and feature support improvements. Ported to SGI Challenge series. VITAL SDF timing data back-annotation and optimized primitives. Current project; one engineer developing SDF parser and timing delay annotator for simulator. Designing simulation and code generation optimizations for primitives. Simulation backplane. Team of 8 engineers. Took over responsibility for a poorly managed project. Although team morale and progress was substantially improved, the project was terminated due primarily to financial pressures and re-focus of company after merger with Viewlogic. ViP Interface. A complex integration with a 3rd party product while that product was under development. Recommended project termination due to high development costs relative to expected return (revenue). </p> <h3>Cadence/Valid, San Jose, CA, 10/90 - 3/92, Principle Engineer</h3> <p>Principle engineer responsible for VHDL product R&D. Providing technical direction to a team of development engineers. Active participation in IEEE VHDL standards activities including VHDL '92 Design Review Team and ISAC (Issues Study and Analysis Committee, which recommends IEEE official interpretation of VHDL standard). In addition to designing, developing and integrating new product features, also assisted marketing in pre-sales support for major customers' evaluations and the analysis of customers' requirements for the VHDL product. Periodically assisted customer support in the analysis and resolution of customer reported problems. </p> <h3>Intermetrics Inc., Bethesda, MD, 1989-1990, VHDL Software Engineer</h3> <p>Member of the VHDL product team with responsibilities for porting the VHDL toolset to the Sun4 platform, developing graphical waveform display tool that supports any user-defined typed signals, bug fixing and performance analysis and enhancement. </p> <h4>Intermetrics Inc., Bethesda, MD, 1988-1989, Project Manager and Tech Marketing</h4> <p>Responsible for the pursuit and development of business opportunities in the areas of software development tools and productivity (CASE tools). Managed and participated in the development of contract proposals. Assisted negotiations with commercial vendors for the integration of Intermetrics' developed technology with vendors' product lines. Supervised an engineering project for the design of a textual-based design and documentation (DOD-Std-2167A) tool for Ada. Company representative to government-industry workshops on standardization and new technology application (NIST - integrated software engineering environments). </p> <h4>Intermetrics Inc., Huntington Beach, CA, 1986-1988, Project Manager and Software Engineer</h4> <p>Project Manager for a small development team (3 engineers) that designed and developed a graphical, object-oriented design tool for Ada (SoftCAD and RSL -- Reusable Software Library). Ported SoftCAD from VAX/VMS and Tektronix platforms to IBM-PC/MS-Windows platform. Developed reverse-engineering front-end to SoftCAD that generated graphical representation of software system through parsing of Ada source. Member of team that designed a real-time, embedded, distributed operating system for avionics applications. Responsible primarily for distributed message communication functionality. Military application with documentation provided to DOD-Std-2167A standards. </p> <h3>Hughes Aircraft Co., 11/85 - 4/86, Software Engineer</h3> <p>Senior Design Team Leader responsible for resolving key design issues concerning the Traffic Management function of the Federal Aviation Administration's Advanced Automation System (air traffic control system). Analysis of software requirements and software design for arrival, en route and departure metering of commercial aircraft. Assisted in the resolution of data security issues within AAS. </p> <h3>U.S. Air Force (highest rank Sgt), March AFB, CA, 8/82 - 9/85, Office Manager</h3> <p>Supervised the day-to-day office operations of the Base Operations and Training Division. Supervised and trained three people. </p> <p>Return to <a href="#resume-index">Index </a></p> <hr> <h2><a name="resume-pubs">PUBLICATIONS</a></h2> <ul> <li><a name="resume-pubs">Bailey, S. and Willis, J., <cite>"Shared Variables in VHDL '93 A Peek into the Past and a Preview of the Future,"</cite> Proceedings of the Fall VHDL Users International Forum (VIUF), Nov 94 (presented). </a></li> </ul> <ul> <li><a name="resume-pubs">Bailey, S., <cite>"Network Modelling in VHDL,"</cite> Proceedings of the Spring VHDL Users International Forum (VIUF), May 92 (presented). </a></li> </ul> <ul> <li><a name="resume-pubs">Bailey, S. and Burton B., <cite>"Realizing Software Productivity Through a Software First Design Process Toolset,"</cite> Proceedings of the Sixth Washington Ada Symposium, June 1989 (presented). </a></li> </ul> <ul> <li><a name="resume-pubs">Bailey, S., Laird, J., Falacara, G., and Angevine, M., <cite>"GENESYS Embedded Software Tailorability,"</cite> Proceedings of the 7th Annual National Conference on Ada Technology, March 1989 (presented). </a></li> </ul> <ul> <li><a name="resume-pubs">Falacara, G., Angevine, M., Laird, J., and Bailey, S., <cite>"A Tool for Ada Run-Time Tailoring,"</cite> Conference Proceedings Ada EXPO '88, October 1988. </a></li> </ul> <ul> <li><a name="resume-pubs">Bailey, S., Burton, B., and Mayes, L., <cite>"A Design Tool to Support the Reuse of Existing Software Components,"</cite> National Conference Proceedings Software Reusability, April 1988 (presented). </a></li> </ul> <ul> <li><a name="resume-pubs">Mayes, L., Burton, B., Wienk, R., Koehler, K., and Bailey, S., <cite>"Integrating Diverse Libraries of Reusable Software,"</cite> Conference Proceedings Software Reusability and Maintainability, March 1987. </a></li> </ul> <ul> <li><a name="resume-pubs">Burton, B., Aragon, R., Bailey, S., Koehler, K., and Mayes, L., <cite>"The Reusable Software Library,"</cite> IEEE Software, July 1987. </a></li> </ul> <p><a name="resume-pubs">Return to </a></p> </li> </dir>  </body>